Defining Anomalous Behavior for Phase Change Memory

Traditional memory systems based on memory technologies such as DRAM are fast approaching their cost and power limits. Alternative memory technologies such as Phase Change Memory (PCM) are being widely researched as a scalable, costand power-efficient alternative for DRAM. However, a PCM memory cell has a limited endurance of 10− 10 writes, resulting in an ideal lifetime of only a few years which can be reduced further due to the non-uniform distribution of write traffic to the main memory. Wear leveling algorithms have been proposed to ensure uniform distribution of traffic to the main memory. However, this limited write endurance poses an easy to exploit loophole for attackers to bring the system down. A malicious application can perform multiple writes to the same memory location (PCM cell) and quickly cross the endurance limit for the cell. We show that wear leveling algorithms, while meeting their objective for non-malicious applications, do not help to protect the system from this exploit. If PCM based systems are to be adopted for future systems, it is critically important that this security hole is addressed. In this paper, we define what constitutes as anomalous behavior for PCM and, in general, for memories with limited write endurance. Once an application is established to exhibit anomalous behavior, solutions can be built on top of it to prevent any reduction in the lifetime of the system due to the main memory reaching its write endurance limit.